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AbiralArch/hardware-cvdp-examples
Updated
Aug 1, 2025
•
29
AbiralArch/hardware-verilogeval-v2
Viewer
•
Updated
Aug 1, 2025
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471
•
38
AbiralArch/hardware-shailja-vgen
Viewer
•
Updated
Aug 1, 2025
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87
•
30
AbiralArch/hardware-cvdp-complete
Updated
Aug 1, 2025
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197
•
1
xxrjun/rtllm-variants
Viewer
•
Updated
Mar 6
•
50
•
4
architect-ubc-capstone/rtl-augmented
Updated
Mar 20
•
171
architect-ubc-capstone/rtl-augmented-v2
Updated
Mar 23
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378
architect-ubc-capstone/rtl-augmented-v3
Updated
Apr 14
•
198
VN-26/rtl-llm-dataset
Updated
Mar 30
•
30
Adel9st/Verilog-Turkish-Dataset
Updated
Apr 22
•
67
billshockley/titanbench
Updated
May 7
•
82
vyomaalabs/verixa-dataset
Viewer
•
Updated
May 30
•
105k
•
40
KSU-HW-SEC/SynthAgentic-Eval
Updated
May 10
•
265
Rajasrl/VLSI-Dataset
Updated
May 13
•
7
EvanOLeary/rtllm-shinka-evolve
Viewer
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Updated
Jun 17
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1.84k
•
18
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1
hasankursun/soc-builder-rtl-v1
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Updated
Jun 30
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5k
•
11.7k
•
2
aashay96/scientific-posttrain-rtl-formal-eval
Preview
•
Updated
Jul 17
•
26
nickh007/hw-verify
Viewer
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Updated
21 days ago
•
49
•
123
theepicflyer/openrtlset-permissive-verified
Viewer
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Updated
17 days ago
•
13.6k
•
72
Jongbin-kr/VeriReason-RTL-Coder_7b_no_reasoning_tb
Viewer
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Updated
9 days ago
•
1.89k
•
55
fenggev566/Reasoning-benchmark-sim-out
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•
Updated
8 days ago
•
150
ssdataanalysis/hebocrbench-v1
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Updated
7 days ago
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34.3k
•
159